The fabrication of integrated circuits (ICs) requires the processing of single-crystal (silicon) wafers in a large number of subsequent process steps. The total set of process steps that belongs to a specific technology is called a “process flow” or just simply a “flow.” During each step, the silicon and other involved materials are structured, modified, transformed or in other ways manipulated. The outcome of one process step is then passed on as input to the next. Prominent examples of process steps in semiconductor fabrication are epitaxy, oxidation, film deposition, lithography, etching, ion implantation, and diffusion.
Each process step is characterized by a great variety of process parameters. These correspond directly to specific equipment settings and/or programs (“recipes”) by which the actual fabrication process is determined and controlled. Examples of process parameters include things like growth- or deposition-rates, the composition of gas flows or chemical etchants, exposure times, etch times, furnace temperatures, implant species, implant energies and doses, bias voltages or currents, wait times, and the like.
Once a technology is fully developed, the corresponding process flow is “frozen.” From then on, all process parameters may only vary within a narrow range around previously defined “target” values. This narrow bandwidth is called the specification range or shortly the “spec range.”
Silicon wafers are typically processed in lots of 25, i.e., groups of 25 wafers receive the same treatment, either because they are indeed simultaneously processed in the same piece of equipment or because they are processed in a short sequence as a batch. To develop or improve a technology, it is fundamental to run experiments at various process steps. Therefore, the wafers of “experimental lots” are split up into groups. Different split groups vary at least at one process step in at least one process condition. Wafers that belong to the same split group undergo the same processing. The term “wafer split” (or simply “split”) is used as synonym for “process experiment” herein.
Whether a wafer lot has been split up or not, once it has passed the last process step, it will be more or less extensively tested. The data is then evaluated and analyzed and the results are fed back into the process flow. For standard production material (with typically no applied splits), this is done in order to monitor the process and to enable failure analysis for development material (typically including a number of different splits) to achieve and/or improve a certain device performance. In the context of the invention, focus is on the latter.
A fundamental feedback loop in semiconductor manufacture involves processing, test, evaluation and analysis. Parametric data analysis, however, quite naturally requires a different evaluation approach for device and process development than for monitoring high-volume production. In standard high-volume production (usually) a great many lots are processed in a uniform manner; whereas the wafer splits during development phases are typically applied on just a restricted number of lots. For development material, however, the application of rather complex experimental split matrices and a largely extended test depth, with parameter numbers easily ranging up to several thousands, literally demand for a new methodology to facilitate data evaluation. Evaluating the impact of experimental splits—not to mention possible cross-dependencies—on such extended numbers of (electrical) parameters is not only prone to errors, but in many cases proves to be impossible for more than just the primary parameters. Conventional statistical methods/concepts, such as correlation calculus, ANOVA, CPK, etc., are valuable, but simply not sufficient. Intelligent data reduction becomes the key to achieve and maintain efficiency (and cost effectiveness).